11 / 37 · Concept

Encoders and priority: choosing one of several requests

Distinguish the input assumption of a one-hot encoder from a priority encoder's valid and selection outputs.

Reversing a decoder also requires conditions

A decoder^{Decoder A circuit that activates the output line corresponding to a binary code. With an enable input, all outputs can be set to 0 when disabled. Learn more} converts an address into one-hot^{One-hot A representation with exactly one bit set to 1. A condition that also permits all zeros is called one-hot-or-zero. Learn more} select lines. An encoder converts the position of an active input into an address. An ordinary one-hot encoder assumes that only one input is active. If several inputs are 1, the specification must say which position to report.

For four request bits $r_3r_2r_1r_0$ , give higher-numbered requests priority. For all-zero inputs, use valid=0 and index=00. Treating index=00 alone as “no request” would confuse it with a request from r0.

Input r3r2r1r0	valid	index
1---	1	11
01--	1	10
001-	1	01
0001	1	00
0000	0	00

A dash means either 0 or 1 gives the same result, not that simulation X inputs are permitted. The patterns, listed from the top, are mutually exclusive.

valid=r_3+r_2+r_1+r_0,\quad index_1=r_3+r_2,\quad index_0=r_3+\overline{r_2}r_1

For 1011, index=11. For 0110, r2 outranks r1, so index=10.

Each column is an independent request combination

View waveform data

Wave data: each character is one interval; a dot holds the previous state; p is a clock cycle.
Signal	Wave	Bus values
requests	`234523`	0000 → 0001 → 0011 → 0110 → 1011 → 1000
valid	`01....`
index	`2.345.`	00 → 01 → 10 → 11

RTL should make priority explicit

SystemVerilog
always_comb begin
  valid = |request;
  index = 2'b00;
  if      (request[3]) index = 2'd3;
  else if (request[2]) index = 2'd2;
  else if (request[1]) index = 2'd1;
end

When only request[0] is 1, the default index=0 and valid=1 apply. Defaults on every path prevent unintended memory in a combinational circuit. Test all 16 inputs: whenever valid=1, the selected request bit must be 1 and every higher-numbered bit must be 0.

Selection and fairness are separate problems

If r3 stays 1, r0 is never selected. This circuit implements fixed priority only. Fair request handling requires arbitration that remembers previous selections, making it a sequential circuit.

Lab · Observe requests, the selected index and grant together

Select one of the simultaneous requests

r3r2r1r0=1011; valid=1; index=11; grant=1000. Higher numbered requests take priority. When valid=0, index does not identify a selected request.

The initial requests 1011 select r3. Turn r3 off: r1 is selected, index=01 and grant=0010. Toggling r0 must not change the selection while r1 remains 1.

Compare “turn all off” with enabling only r0. Both give index=00, but valid and grant differ. A downstream circuit that reads only index could process a nonexistent request.

The grant vector, whose only 1 marks the selected request, is a decoding of index and valid:

grant_i=valid\land(index=i)

Check three invariants: grant contains at most one 1; every granted position actually has a request; and all requests above the selected index are 0. This lab neither consumes requests nor remembers earlier selections. Lower requests waiting while r3 stays on demonstrate fixed-priority behavior.

Try it yourself

Give index, valid and grant for requests 0101 and 0001. Why must you not process r0 for requests 0000 merely because index=00?

Read the explanation

For 0101: index=10, valid=1, grant=0100. For 0001: index=00, valid=1, grant=0001. For 0000, index=00 is only a default; valid=0 and grant=0000 mean there is no request to process.