Waveform sampling times and causality

Events have an order even at one timestamp

Signals appearing to change at the same timestamp do not change simultaneously without causes. An event-driven RTL simulator settles values after processing active events, nonblocking^{iNonblocking assignment An assignment written as <= in sequential RTL. It evaluates the right-hand side and schedules the update, allowing registers at the same edge to compute from the previous state. Learn more} updates and other scheduled events. Physical devices change after clock-to-Q and combinational propagation delays^{iPropagation delay The time from an input change until the output settles to the correct value. Logical equivalence and timing behavior are separate properties. Learn more}. Interpret these as different models.

For this lab, build a prediction table using input application → combinational evaluation → rising-edge^{iRising edge The instant at which the clock changes from 0 to 1. Distinguish it from a level, which refers to the entire interval during which CLK=1. Learn more} capture → state update. Check both the tool's input-application time and its result-recording time.

The actual simulator's event schedule and recording points matter. The four steps below are distinctions needed for the prediction table, not four clock periods.

Calculate independent expected values first

Calculate y for each input group, then use separate columns to identify the edge at which it appears in q. The first differing row between expected and actual results helps localize the cause to input application, selection logic or storage behavior.

Distinguish transitions from settled behavior

If both data inputs are equal while the select changes, the final output should remain the same, but unequal internal path delays can cause a short glitch. Conversely, not every normal transition to a different result is a glitch. Logical waveform comparison and physical timing analysis answer different questions.

In a conventional testbench, changing stimulus and immediately reading outputs at the DUT's rising edge can create a race. Separate driving and observation, or use explicit synchronization such as clocking blocks. The provided DDS lab uses input JSON and the tool's single-clock rules; do not add an arbitrary #delay testbench.