Flip-flops, enable and control priority

A register stores the result of a next-state function

Let $Q_k$ be the value just before the clock edge, $D_k$ the input accepted at that edge, and $Q_{k+1}$ the updated value. A register^{iRegister A circuit that stores multiple bits of state. The synchronous registers in this course store their specified inputs at a clock edge. Learn more} with reset before enable follows

When enable is 0, changes to D do not change the stored value. Omitting this hold path in sequential RTL differs from omitting an assignment in combinational logic. Holding state is part of the register's specification.

module enabled_register (
  input logic clk, rst, en,
  input logic [7:0] d,
  output logic [7:0] q
);
  always_ff @(posedge clk) begin
    if (rst) q <= 8'b0;
    else if (en) q <= d;
  end
endmodule

This is a synchronous active-high reset. At an edge where reset and enable are both 1, the circuit stores 0. Reversing the priority changes the function, so capture priority in code and tests, not only in comments.

Each column below records one rising edge^{iRising edge The instant at which the clock changes from 0 to 1. Distinguish it from a level, which refers to the entire interval during which CLK=1. Learn more}. Inputs are sampled just before the edge; a state labeled “after” is its value immediately after the update. Column alignment shows sample order, not physical propagation delay^{iPropagation delay The time from an input change until the output settles to the correct value. Logical equivalence and timing behavior are separate properties. Learn more}. Initial Q=0xA5. The first column holds, the second writes, and the third has simultaneous reset and enable.

Enable does not mean directly chopping the clock

Using an arbitrary combinational expression such as gated_clk = clk & en as a clock can create short pulses or unintended edges when en changes. Mapping clock-enable RTL to cells is the responsibility of synthesis and implementation. Clock gating for power reduction is designed separately with appropriate cells and timing verification.

Control priority becomes visible when reset, load, enable and similar controls overlap. Activating them only one at a time is insufficient. For example, starting from q=A5, en=0 with d=3C must hold the value; en=1 at the next edge must store 3C.