State machines: separating state, transitions and outputs

State summarizes only the history that matters

Define stored state when present inputs alone do not determine outputs. Instead of retaining all input history, distinguish only the past differences needed to determine future behavior.

Consider a controller for starting and completing work. IDLE waits for requests, BUSY processes work, and DONE indicates completion for one cycle.

busy and done are outputs of the current state. For example, after the edge that observes completion in BUSY, state becomes DONE and done becomes 1. These are Moore outputs.

Each column below records a rising edge^{iRising edge The instant at which the clock changes from 0 to 1. Distinguish it from a level, which refers to the entire interval during which CLK=1. Learn more}. Inputs are pre-edge; states labeled “after” are post-update. Alignment shows sample order, not physical propagation delay^{iPropagation delay The time from an input change until the output settles to the correct value. Logical equivalence and timing behavior are separate properties. Learn more}. Starting in IDLE, the edge accepting work_done leads to DONE and done=1. DONE always leads to IDLE, regardless of start.

RTL separating transitions from storage

typedef enum logic [1:0] {IDLE, BUSY, DONE} state_t;
state_t state, next_state;
always_comb begin
  next_state = state;
  case (state)
    IDLE: if (start) next_state = BUSY;
    BUSY: if (work_done) next_state = DONE;
    DONE: next_state = IDLE;
    default: next_state = IDLE;
  endcase
end
always_ff @(posedge clk)
  if (rst) state <= IDLE;
  else state <= next_state;
assign busy = (state == BUSY);
assign done = (state == DONE);

This SystemVerilog example illustrates the control structure. The connected worker's work_done generation and input synchronization must be implemented separately.

Questions easily omitted from a specification

This circuit ignores start in BUSY and DONE. To accept a new request at completion, revise the transition table first. A Mealy output uses both state and current input and can respond quickly, but its combinational timing and glitches need review. Choosing binary versus one-hot^{iOne-hot A representation with exactly one bit set to 1. A condition that also permits all zeros is called one-hot-or-zero. Learn more} state encoding is independent of choosing Moore versus Mealy outputs.