logic, wire, X/Z and explicit bit widths

Type, driver and storage are separate questions

logic is a four-state data type. wire describes a net connection; a net can carry four-state logic values too. A logic variable may be used for a combinational result or clocked state, subject to the language’s driver rules. Neither spelling alone promises a flip-flop. Identify the actual continuous assignment, combinational procedure or edge-triggered procedure.

Use one intended driver for each ordinary RTL signal. Resolved multi-driver nets and bidirectional interfaces require a separate electrical and tool contract; they are not part of this course’s single-driver examples.

State the width and interpretation

logic [7:0] u holds eight bits interpreted as unsigned. logic signed [7:0] s holds the same number of bits interpreted as signed two’s complement. The bit pattern 8'hFF means 255 for u and −1 for s. A packed vector transfers its bits together; it is not an eight-element time sequence.

module typed_examples (
  input  logic [3:0] a, b,
  input  logic signed [7:0] s,
  output logic [4:0] full_sum,
  output logic signed [8:0] extended_s,
  output logic negative,
  output logic any_bit, all_bits, parity
);
  assign full_sum = {1'b0, a} + {1'b0, b};
  assign extended_s = {s[7], s};
  assign negative = s < 8'sd0;
  assign any_bit = |a;
  assign all_bits = &a;
  assign parity = ^a;
endmodule

The concatenation for extended_s repeats the sign bit. Merely adding a leading zero would turn −1 into +255. Concatenations are unsigned expressions, so signed arithmetic on a concatenation needs an explicit signed interpretation or a suitably declared intermediate. In this example it is assigned into the signed destination with the intended bit pattern.

Use sized literals when the design depends on width. 4'd15, 8'hFF and 8'sd0 make width and, where needed, signedness visible. An unsized integer literal can widen an expression. Inspect both operands and the assignment context rather than assuming the left operand decides every result type.

Distinguish three families of operators

a & b combines corresponding bits. a && b asks whether both vectors are logically true and yields a one-bit result. &a reduces one vector and asks whether all its bits are 1. For a=4'b0011 and b=4'b0101, these are 0001, 1 and 0. ^a is parity; it is 0 for 0011.

For a simple teaching RTL block, separate intermediate expressions when their widths or signedness are unclear. Readability is a verification aid: it lets you write a precise range for each signal.

Unknown is not a third physical voltage

X models an unknown value and Z a high-impedance drive state. They are simulation values, not exact physical voltages. A two-state execution model cannot establish four-state behavior. Reset unknown state deliberately in a four-state testbench instead of masking every X to zero.

== can yield X when equality cannot be determined. In a testbench, actual !== expected produces a definite mismatch when an expected known value is compared with X/Z. Do not use case equality to claim that physical X values can be detected by ordinary hardware.

Practice · Extend, add and compare

Check a=15,b=1: full_sum=5'b10000. Check s=8'h80: extended_s=9'b110000000 and negative=1. Check s=8'h7F: extended_s=9'b001111111 and negative=0. Test zero, the positive maximum, the negative minimum and −1 separately.

Change extended_s to {1'b0,s} and verify that the negative cases fail. Change a testbench comparison from !== to !=, inject X into actual, and inspect whether the conditional reliably reports failure. A check that becomes unknown can silently miss the intended assertion.