Altifigence Academy

6 / 37 · Concept

Vector indexing, bit order and signedness

Separate bit numbering, serial transmission order and arithmetic interpretation when reading datapaths.

An index is a name; declaration direction determines its meaning

In logic [7:0] a;, a[7] is the leftmost position. In logic [0:7] b;, b[0] is leftmost. Assigning 8'h96 to both gives the same left-to-right pattern, 10010110, but different indices for each bit. The assumption “bit 0 is always the LSBLSB The bit with the lowest place value. Check both the notation direction and the indexing rules.” is valid only after checking declaration direction.

In practice, consistent direction throughout an interface makes review easier. Also specify waveform display order and bit-array order in files. This course's input JSON arrays are LSB first, while RTL vector displays are generally read MSBMSB The bit with the highest place value. Its index depends on the vector's declaration direction, so do not assume it always has the largest index. first.

Verify shift direction from the actual connections

In q <= {q[1:0], din};, next q[2] is old q[1], next q[1] is old q[0], and next q[0] is din.

q2next=q1,q1next=q0,q0next=dq_2^{next}=q_1,\quad q_1^{next}=q_0,\quad q_0^{next}=d

Which index receives which signal is a more precise specification than whether a diagram points left.

The arrows below show the storage positions a bit traverses. Every registerRegister A circuit that stores multiple bits of state. The synchronous registers in this course store their specified inputs at a clock edge. Learn more reads old values at the same edge. They do not imply that din passes all the way to q2 in one edge.

Read the shift path by bit number
  1. din: Bit accepted at this edge
  2. q0: Capture din
  3. q1: Capture previous q0
  4. q2: Capture previous q1

Arithmetic and logical shifts

>> is a logical right shift that fills the vacant left, most significant positions with zeros. >>> can implement an arithmetic right shift with sign extension when its left operand is signed. Identical bits can produce different results depending on the operand's signed declaration.

SystemVerilog
logic signed [7:0] x;
logic [7:0] logical_right, arithmetic_right;
assign logical_right = x >> 1;
assign arithmetic_right = x >>> 1;

For x=8'b11111000 (-8), the results are 01111100 and 11111100 respectively. Arithmetic right shifting a negative number does not always follow the same rounding rule as signed integer division; check this separately in numerical algorithms.

Try it yourself

For three-bit q=101 and din=0, find the next values of q<={q[1:0],din} and q<={din,q[2:1]}.

Read the explanation

Both expressions give 010. The two directions happen to agree for this input. With q=001 and din=0, they give 010 and 000, revealing a direction error.

Your choice applies to this browser. Change it any time using the footer.