12 / 37 · Concept

MUX verification: exhaustive tests and properties

Check combinational input coverage separately from storage behavior, and minimize counterexamples.

What will count as correct?

One-bit data a, b and select sel have eight combinations. At this size, checking every case is efficient. Exhaustively testing an entire width-W MUX^{Multiplexer A combinational circuit that connects one of several inputs to the output according to a select signal. Specify how select bits map to input numbers. Learn more} takes $2^{2W+1}$ combinations including select, so wider designs soon need another strategy.

For a width-W output, each bit follows

\forall i\in\{0,\ldots,W-1\},\quad y_i=\overline s a_i+s b_i

Choose stimuli for the faults you want to detect

Fault to check	Useful input or observation
Swapped a/b connections	Make a and b different and compare sel=0 and 1
Reversed bit order	Walking-one patterns with one bit set
Stuck-at fault	All zeros, all ones and alternating patterns
Incorrect storage edge	Change inputs between edges and check that q holds
One-cycle latency error	Make expected values differ at consecutive edges

A large test count alone does not make verification effective. Be able to explain which faults each test detects.

The comparison below selects only cases where a and b differ. Each column is one test vector. The reversed selection expression produces the opposite of expected in all four columns.

Four combinations exposing reversed selection

View waveform data

Wave data: each character is one interval; a dot holds the previous state; p is a clock cycle.
Signal	Wave	Bus values
a	`0.1.`
b	`1.0.`
sel	`0101`
expected	`01.0`
swapped bug	`10.1`

Keep the reference model independent of the implementation

Copying DUT code can implement the same mistake twice. Generate expected values from the specified truth table^{Truth table A table listing every possible input combination and its output. Changes over time are checked separately with waveforms. Learn more} or indexed selection, and track q's earlier captured state separately. When a mismatch occurs, shorten the input sequence while preserving the failure, then explain the cause.

Instead of testing only final state, record actual value, expected value and inputs at every observation point. These records distinguish “the simulation ran” from “the specification was satisfied.”

Try it yourself

For an eight-bit MUX, you tested both select values only with a=0x00 and b=0xFF. Can this also detect reversed output bit order?

Read the explanation

No. Reversing the bit order leaves 0x00 and 0xFF unchanged. Choose position-sensitive patterns such as 0x01 and 0x02 and compare every output bit.