2 / 37 · Concept

Signals and ports: a contract for width, direction and time

Read interfaces and distinguish the checking criteria for combinational and state outputs.

Read a port list as a circuit contract

input logic [7:0] data is a port that transfers eight bits simultaneously, not eight values arriving in sequence. The logic type alone does not create a storage element. Combinational assignments versus edge-triggered sequential blocks determine hardware behavior.

When reading a signal, check width and direction, but also when it is valid, who drives it and its value after reset. Without that information, individually correct modules can form an incorrect system.

The same MUX can expose two kinds of output

This course's lab observes both the selected result y and its stored version sampled_y.

y(t)=\overline{s(t)}a(t)+s(t)b(t)

q_{k+1}=y(t_k^-)

The first equation describes the combinational function; the second is an ideal synchronous model that captures stable y just before an edge. Comparing both outputs unconditionally against the inputs at the same instant can falsely flag a correct register^{Register A circuit that stores multiple bits of state. The synchronous registers in this course store their specified inputs at a clock edge. Learn more} as erroneous.

SystemVerilog
assign y = sel ? b : a;
always_ff @(posedge clk) sampled_y <= y;

A simulator orders events even within the same time value. A physical device has setup^{Setup The minimum time that input data must be stable before the capturing clock edge. If it is violated, the stored result is not guaranteed. Learn more}/hold requirements and clock-to-Q delay. These equations do not erase those differences; they establish explicit observation points for functional verification.

The arrows show data dependencies. Changes to a, b or sel first affect combinational y, while sampled_y captures a new value only on a rising edge^{Rising edge The instant at which the clock changes from 0 to 1. Distinguish it from a level, which refers to the entire interval during which CLK=1. Learn more}.

The boundary between combinational and stored outputs

a · b · sel: Inputs presented simultaneously
MUX → y: Compute using the current select signal
DFF → sampled_y: Capture y at the rising edge

Questions to review

Is sel a known 0/1 input or an asynchronous external signal?
After y changes, is the comparison with sampled_y made after the next valid edge?
Does reset^{Reset A control that returns state to a specified initial value. Define whether it is synchronous or asynchronous and whether it has priority over other controls. Learn more} define sampled_y's initial value, or does it come from a tool initialization setting?

The explicit initial value in this lab configures a reproducible 0/1 model. It must not be interpreted as a guarantee of a physical chip's power-up behavior.

Try it yourself

Between clock edges, a changes from 0 to 1 while sel remains 0. When do y and sampled_y change?

Read the explanation

Combinational y changes after the relevant combinational evaluation or propagation. sampled_y updates at the next rising edge that captures that value. Input changes near an edge raise setup/hold concerns in real circuits, so this simple model alone cannot establish safety.