Compile, lint and synthesis: what diagnostics establish

Establish what the tool was asked to check

A result is meaningful only with a source list, selected top, parameter settings, language mode and tool version. Compile the circuit with its dependencies; compile a testbench as a separate simulation top. Do not synthesize the testbench’s clock generator or mistake an uninstantiated module for the tested design.

The examples in this course use a practical synthesizable SystemVerilog subset. General-purpose simulators and product engines may support different subsets. Check the actual diagnostics and supported front end rather than assuming the .sv extension enables every language feature.

Compile checks structure, simulation checks exercised behavior

Compilation can reject syntax errors, missing modules and invalid references. It does not prove the chosen arithmetic or reset priority. The testbench then compares behavior under the supplied scenarios. A PASS line supports those comparisons with that source and tool; it is not universal correctness.

For the parameter lab:

iverilog -g2012 -s tb -o sim.vvp modulo_tick.sv tb.sv
vvp sim.vvp

Record both exit statuses. Running an older sim.vvp after a failed compile can report a misleading PASS. Produce a fresh output for each configuration and stop if compilation fails.

Review diagnostics by cause

Do not suppress every warning to obtain a clean log. Either repair the cause or document a narrow, intentional exception with a test. A tool’s warning category and severity may differ across versions.

Verilator offers a separate lint workflow; its official warning reference explains diagnostics such as WIDTH and LATCH. If Verilator is installed, a simple entry command is:

verilator --lint-only --top-module periodic_accumulator modulo_tick.sv periodic_accumulator.sv

This command is an additional tool path, not a claim that Verilator was used in your run. Keep the actual executed commands distinct from suggested commands.

Synthesis is another boundary

A generic Yosys check for the integrated DUT can be run with:

yosys -p 'read_verilog -sv modulo_tick.sv periodic_accumulator.sv; hierarchy -check -top periodic_accumulator; proc; opt; check -assert; stat'

This tests the front end and generic circuit structure. It does not provide a target FPGA resource report, placement, routing, timing closure or manufacturing acceptance. A technology mapping and constraints flow would be additional work.

Practice · Keep failing examples outside the delivered DUT

Make three disposable copies: misspell the child module name; truncate a nine-bit sum into eight bits; omit an output assignment from a combinational branch. Check which tool catches each issue and which needs a functional test. A width warning can be intentional; a latch can even compile successfully. The correct comparison is between the requirement and the implemented behavior.

Retain one relevant deliberate-failure log alongside the restored passing source. Record unexplained diagnostics as unresolved findings rather than calling the result clean.