Widths of slices, concatenations and replications

Concatenation is not addition

{a,b} appends b's bits after a's bits. If their widths are M and N, the result width is M+N. For two unsigned^{iUnsigned A rule for interpreting a bit pattern as a nonnegative integer. The n-bit range is 0 through 2^n−1 and may differ from the signed interpretation of the same bits. Learn more} bit patterns, numerically

With a=2'b10 and b=3'b101, concatenation gives 5'b10101, or 21, not the arithmetic sum 7.

a's bits move upward by b's width. Read this concatenation^{iConcatenation An operation that joins bit patterns side by side. Its result width is the sum of the operand widths; it is not numerical addition.} as a×2³+b, not a+b.

Write the width beside each expression

logic [7:0] word;
logic [3:0] upper, lower;
logic [7:0] swapped;
assign upper = word[7:4];
assign lower = word[3:0];
assign swapped = {lower, upper};

Input 8'hA3 gives swapped=8'h3A. An incorrect slice^{iSlice An operation selecting a contiguous range of bits from a vector. The selected range determines the result width and bit order.} boundary changes the width or value. A part-select can be treated as a separate unsigned value even when the original vector is signed, so recheck its meaning before signed arithmetic.

Sign extension and replication

logic signed [3:0] small;
logic signed [7:0] extended;
assign extended = {{4{small[3]}}, small};

Concatenate four copies of the sign bit with the original four bits to make eight. Sign extension is not adding 1 because the MSB^{iMSB The bit with the highest place value. Its index depends on the vector's declaration direction, so do not assume it always has the largest index. Learn more} is 1; it widens the bit representation while preserving the interpreted value.

A generic shift circuit using q[N-2:0] has an invalid range at N=1. Restrict the minimum supported width or handle N=1 in a separate generate branch. Parameterization is more than replacing numbers with variables.