Design check: selection equivalence and observation timing

Read the conditions and draw the event order

The combinational output is $y=\overline s a+sb$, and sampled_y captures y at a rising edge^{iRising edge The instant at which the clock changes from 0 to 1. Distinguish it from a level, which refers to the entire interval during which CLK=1. Learn more}. Assume $a=1,b=0,s=0$ has already been captured once. Then change s to 1 between clock edges.

The question asks for values after inputs and combinational logic have settled, before the next rising edge. Functional equivalence and a register's^{iRegister A circuit that stores multiple bits of state. The synchronous registers in this course store their specified inputs at a clock edge. Learn more} observation timing are separate verification items.

Below is the observation order for these conditions, with a=1 and b=0. In the interval where the combinational and stored outputs differ, explain which signal represents present inputs and which represents an earlier capture.

Further design questions

1. Prove with all eight combinations that y=(a & ~s) | (b & s) is equivalent to a one-bit MUX^{iMultiplexer A combinational circuit that connects one of several inputs to the output according to a select signal. Specify how select bits map to input numbers. Learn more}.
2. If sampled_y is removed, the functional equation remains. Explain which temporal behavior disappears.
3. Explain why ideal RTL values alone cannot guarantee physical hardware behavior when the s transition and rising edge are too close.