33 / 37 · Concept

Setup, hold and timing budgets

Separate maximum and minimum path delays and calculate hold requirements independently of clock frequency.

Correct data must also arrive on time

A synchronous path consists of a launch flip-flop^{Flip-flop An element that captures its input at a specified clock edge and holds it until the next edge. The input must meet setup and hold requirements. Learn more} → combinational logic → capture flip-flop. In a simple model with zero clock skew, the setup^{Setup The minimum time that input data must be stable before the capturing clock edge. If it is violated, the stored result is not guaranteed.} condition is below. Uncertainty conservatively accounts for jitter, design margin and related effects.

T_{clk}\ge t_{cq,\mathrm{max}}+t_{pd,\mathrm{max}}+t_{setup}+t_{uncertainty}

$t_{cq}$ is clock-to-Q delay and $t_{pd}$ the maximum combinational delay. Only the time remaining after the source register^{Register A circuit that stores multiple bits of state. The synchronous registers in this course store their specified inputs at a clock edge. Learn more} produces data and the destination reserves setup time is available for combinational logic.

Calculate a path limit numerically

For clock-to-Q=0.12 ns, combinational delay=1.80 ns, setup=0.15 ns and uncertainty=0.08 ns, the minimum period is 2.15 ns.

f_{\mathrm{max}}\le\frac{1}{2.15\ \mathrm{ns}}\approx465.1\ \mathrm{MHz}

500 MHz corresponds to 2 ns, giving setup slack of -0.15 ns. This example concerns one specified path and its assumptions. Guaranteeing an actual operating frequency requires checking every relevant path, corner and constraint.

Follow the delay terms added in series below: their sum is 2.15 ns. Arrows show the budget-addition order, not device sizes or proportional delays.

The path consuming the setup budget

Launch FF: clock-to-Q: 0.12ns
Combinational path: Maximum delay: 1.80ns
Capture requirement: setup: 0.15ns
Design margin: uncertainty: 0.08ns

Hold concerns the fastest path

If launched data changes too quickly at the same edge, it intrudes on the time the receiving flip-flop needs to capture the previous value. With skew=0 and no additional margin, a simple hold condition^{Hold time The minimum time that input data must remain stable after the capturing clock edge. Check the context to distinguish it from ordinary value retention.} is

t_{cq,\mathrm{min}}+t_{cd,\mathrm{min}}\ge t_{hold}

Minimum clock-to-Q=0.05 ns, minimum combinational delay=0.03 ns and hold=0.10 ns leave a 0.02 ns shortfall. Lengthening the period does not fix this same-edge condition. Implementation changes such as added data delay or clock-path adjustment are needed.

Positive skew, with capture clock later than launch clock, can help ordinary single-cycle setup but hurt hold. Draw data arrival and capture edges on a timeline instead of memorizing signs. Do not use multicycle or false-path exceptions merely to silence timing warnings without a functional justification.

Try it yourself

For a 4 ns period, $t_{cq}=0.2$ ns, $t_{setup}=0.3$ ns and uncertainty=0.1 ns, what maximum combinational delay is allowed? Does changing the period to 8 ns fix a hold violation?

Read the explanation

The allowed maximum is $4-0.2-0.3-0.1=3.4$ ns. Increasing the period does not fix the usual same-edge hold requirement. Analyze minimum data-path delay and clock arrival times separately.