Modulo and saturating counters, and terminal pulses

Three distinct policies for exceeding the range

Even for the same N-bit register^{iRegister A circuit that stores multiple bits of state. The synchronous registers in this course store their specified inputs at a clock edge. Learn more}, the specification decides whether to wrap, hold the maximum or report an error.

An eight-bit modulo counter that goes from 255 to 0 differs from a saturating counter that stays at 255. An accumulator requiring both negative and positive values must also account for the signed range and both saturation boundaries.

Each column below records one rising edge^{iRising edge The instant at which the clock changes from 0 to 1. Distinguish it from a level, which refers to the entire interval during which CLK=1. Learn more}. Inputs are pre-edge; states labeled “after” are post-update. Alignment shows sample order, not physical propagation delay^{iPropagation delay The time from an input change until the output settles to the correct value. Logical equivalence and timing behavior are separate properties. Learn more}. Initially count=8, reset=0 and enable=1. The same inputs produce different trajectories for modulo-10, four-bit wraparound and four-bit saturation.

Compare against the final modulo-M state

To produce a pulse every ten enabled edges, use states 0–9 and count only valid edges with enable. Register pulse to mean “this edge consumed state 9 and returned to 0.”

always_ff @(posedge clk) begin
  if (rst) begin
    count <= 4'd0;
    pulse <= 1'b0;
  end else begin
    pulse <= 1'b0;
    if (en) begin
      if (count == 4'd9) begin
        count <= 4'd0;
        pulse <= 1'b1;
      end else count <= count + 4'd1;
    end
  end
end

The default pulse assignment returns it to 0 on the next edge. Simply outputting count==9 can leave it high for several cycles when enable=0 stalls the counter. Distinguish a terminal state from a completion event.

Define how the period is counted

Starting at count=0 after reset, the first pulse occurs after ten edges with enable=1. Whether the first edge is called 0 or 1 matters less than using consistent input, state and output table definitions.

The model below is modulo-16. Starting at 1110, one edge gives 1111 and the next 0000. Pause at 1111 with enable=0. Hold and saturation may display the same value but behave differently on resumption. Compare what a saturating counter should do under the same conditions.