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RTL Design Fundamentals

Learning outline

Learning outline
01RTL and module contracts
RTL: describing concurrent circuitsConcept
Signals and ports: a contract for width, direction and timeConcept
Modules, ports and instances: connections as contractsConcept
Check: combinational and stored outputsCheck
02Types, widths, signedness and expressions
logic, wire, X/Z and explicit bit widthsConcept
Vector indexing, bit order and signednessConcept
Widths of slices, concatenations and replicationsConcept
Two's complement, sign extension and overflowConcept
Check: range and explicit extensionCheck
03Complete combinational RTL and verification
Combinational RTL and complete assignmentsConcept
Encoders and priority: choosing one of several requestsConcept
MUX verification: exhaustive tests and propertiesConcept
Design check: selection equivalence and observation timingCheck
04State, assignments and reset priority
Flip-flops, enable and control priorityConcept
Nonblocking assignments and simultaneous state updatesConcept
Modulo and saturating counters, and terminal pulsesConcept
Lab: verify counter reset, wraparound and invariantsLab
Design check: boundaries of width, priority and wraparoundCheck
05Parameters and static structure generation
parameter, localparam, $clog2 and boundary configurationsConcept
generate: building static circuits with loopsConcept
function automatic and reusable expressionsConcept
Check: N=1 and bit widthCheck
06Testbenches and independent verification
Waveform sampling times and causalityConcept
Lab: a testbench that reports its own failuresLab
Verification plans, coverage and independent reference modelsConcept
Counter debugging and minimal counterexamplesConcept
Check: reference models and racesCheck
07Module composition and integrated lab
State machines: separating state, transitions and outputsConcept
Capstone: an overlapping 101 pattern detectorConcept
Ready/valid and a one-entry elastic bufferConcept
Multiply-add pipelines and data alignmentConcept
Integrated lab: periodic pulses and an enabled accumulatorLab
08Tool diagnostics and the scope of results
Setup, hold and timing budgetsConcept
Clock-domain boundaries and metastabilityConcept
Compile, lint and synthesis: what diagnostics establishConcept
Execution records and continuing into DDS practiceConcept
Final check: functional passes and execution evidenceCheck

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