Widths, sign extension, and overflow

Separate a bit pattern from its meaning

The eight-bit pattern 1111_1101 represents unsigned 253 or signed two's-complement -3. Its stored bits are identical, but comparisons and extensions differ. An eight-bit signed value ranges from -128 to 127; an unsigned value ranges from 0 to 255. Width chooses the number of representable patterns, while signedness chooses their numeric interpretation.

Zero-extend unsigned 253 when moving it to sixteen bits. Sign-extend -3 by repeating its original most significant bit, producing 1111_1111_1111_1101. Zero-extension would change -3 into 253. In SystemVerilog, explicitly establish operand types and widths before calculating; do not assume a concatenation or part-select preserves the signed interpretation you intended.

logic [7:0] ua, ub;
logic [8:0] usum;
logic signed [7:0] sa, sb;
logic signed [8:0] sax, sbx, ssum;
assign usum = {1'b0, ua} + {1'b0, ub};
assign sax = {sa[7], sa};
assign sbx = {sb[7], sb};
assign ssum = sax + sbx;

Here both inputs become nine bits before addition. Unsigned 255+1 gives 256, then zero in the low eight bits. Signed 127+1 also gives mathematical 128, but narrowing to signed eight bits produces -128. Carry reports an unsigned boundary; signed overflow reports a signed boundary. Adding same-sign operands with a changed result sign indicates signed overflow. Adding -1 and 1 can produce carry without signed overflow.

Plan intermediate widths too. The largest unsigned eight-bit product is 65025 and needs sixteen bits. Four unsigned eight-bit values can sum to 1020, requiring ten bits. Truncating every partial sum to eight bits loses information that a wider final register cannot recover.

Use Verilator's WIDTH warnings to investigate unintended size changes. The Node checks in this course execute numeric models, not these HDL snippets. Test zero, extremes, and mixed signs before treating typical positive examples as evidence of correctness.