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RTL Design: Datapaths & Pipelines

Learning outline

Learning outline
01Numeric and arithmetic contracts
Turn an equation into a datapath contractConcept
Widths, sign extension, and overflowConcept
Lab: an eight-bit ALU reference modelLab
Check: carry versus signed overflowCheck
02Register transfers and control
Read register transfers at clock edgesConcept
Schedule shared resources with an FSMConcept
Timing contracts for memory requests and responsesConcept
Check: preserving a completed resultCheck
03Pipeline timing and throughput
Store the complete transaction at pipeline boundariesConcept
Latency, throughput, and initiation intervalConcept
Lab: trace two stages and bubblesLab
Check: what II=1 meansCheck
04Ready-valid flow control
Acceptance events and stability during stallsConcept
Design a one-slot elastic registerConcept
Lab: check 1024 stall patternsLab
Check: counting a stalled transactionCheck
05FIFO and hazard boundaries
FIFO empty, full, and simultaneous transfersConcept
Dependencies, resource hazards, and forwardingConcept
Maintain transaction accounting through flush and resetConcept
Check: replacement in a full FIFOCheck
06Verification and a streaming calculator
Combine a scoreboard with local invariantsConcept
Capstone lab: a FIFO and two-stage streaming calculatorLab
Measure performance and review the designConcept
Final check: lossless stalls and drainCheck

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