6 / 24 · Concept
Schedule shared resources with an FSM
Accumulate four values with one adder while defining state transitions and capture.
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Control state expresses an operation schedule
A shared resource requires operations to be scheduled over time. Consider summing x0 through x3 with one adder and a ten-bit accumulator. Capture all four operands when a request is accepted. Later external changes must not alter an outstanding request. The controller selects an operand, enables accumulation, and decides when the result becomes valid.
Use states IDLE, ADD0, ADD1, ADD2, ADD3, and DONE. The acceptance edge in IDLE captures inputs and clears acc. The next four edges add one stored operand each. Immediately after the ADD3 edge, the final sum is stored and state becomes DONE. DONE holds the result until the consumer accepts it. This simple version returns to IDLE at that edge and does not simultaneously accept a new request.
| Edge | Old state | Action | New acc |
|---|---|---|---|
| 0 | IDLE | Capture 3,5,7,9 and clear acc | 0 |
| 1 | ADD0 | Add 3 | 3 |
| 2 | ADD1 | Add 5 | 8 |
| 3 | ADD2 | Add 7 | 15 |
| 4 | ADD3 | Add 9, enter DONE | 24 |
| 5 | DONE | Consumer accepts result | 24 |
Distinguish becoming available after edge 4 from transferring at edge 5. Consumer stalls can extend DONE indefinitely. Resource reuse reduces arithmetic hardware, but limits throughput compared with a pipeline accepting every cycle. Supporting simultaneous completion and a new request requires an explicit priority between old-result delivery and new-request initialization.
- IDLE: Accept and capture all four values
- ADD0..ADD3: Reuse one adder on four edges
- DONE: Hold the result until consumed
Derive controls from state: accumulator enable in ADD states, an operand selection matching the state, and result valid in DONE. Give combinational control outputs defaults. Define acceptance so a continuously asserted request does not repeat accidentally. Reset returns to IDLE and discards outstanding work. A counter-based implementation can reduce the state encoding, but still needs the same edge-by-edge schedule.
Try it yourself
What are acc values after ADD0 through ADD3 for four inputs of 255? What must happen when output ready is zero at edge 5?
Read the explanation
Values are 255, 510, 765, and 1020, all fitting ten bits. With ready=0, no delivery occurs; hold DONE, acc=1020, and valid=1.