Read register transfers at clock edges

All registers read the old state

Start by identifying information that must survive between cycles. An accumulator, captured operands, a loop count, and output valid are state. The sum of current accumulator and operand is a combinational value. Writing a variable does not by itself explain storage; specify the event that captures its value.

This accumulator adds x only on rising edges with en asserted. With en low, it holds its value. A nine-bit intermediate makes the addition explicit; selecting its low eight bits defines modulo-256 behavior. Nonblocking assignments in always_ff schedule next state using the values read at the current edge. Reading the block as immediate software assignments gives the wrong interpretation when multiple registers are involved.

logic [7:0] acc;
logic [8:0] next_sum;
assign next_sum = {1'b0, acc} + {1'b0, x};
always_ff @(posedge clk) begin
  if (rst) acc <= 8'd0;
  else if (en) acc <= next_sum[7:0];
end

Reset is synchronous and takes priority over enable. Omitting a sequential assignment when en is low means register hold. Omitting an assignment on a combinational path can instead imply an unintended latch. For combinational next-state logic, give defaults and then override them for specific conditions.

At edge 2, the visible input 100 was not accepted. At edge 3, 7+250=257 narrows to 1. Distinguishing presentation from acceptance remains essential when en later becomes valid AND ready.

For a<=x; b<=a;, old a=5 and x=9 produce new a=9 and b=5. If b should receive 9, connect its input to x. Complete the old-state column first, then calculate all next-state values together; this exposes one-cycle mismatches between data and control.