Store the complete transaction at pipeline boundaries

A register boundary carries meaning as well as bits

Split f(a,b)=3(a+b) into two stages. Stage one stores a nine-bit sum of two unsigned eight-bit operands. Stage two forms an eleven-bit scaled value and stores its low eight bits. The maximum wide result is 1530. Narrowing the intermediate sum happens to preserve the final modulo-256 value for this integer expression, but would lose information needed by overflow reporting or later comparisons. Keep the intermediate width explicit.

Each stage stores valid and tag with data. Valid zero denotes a bubble. Old data bits may remain in an empty stage, but they must not count as a transaction. A tag requires the same register delay as its value. Two data registers with only one tag register attach transaction B's identity to transaction A's result.

This core assumes no stalls and always-ready ports. Extend s1 and size the constant before multiplication. The second stage reads old s1 and t1; the new input cannot pass through both registers at one edge.

logic [8:0] s1;
logic [7:0] s2, t1, t2;
logic v1, v2;
logic [10:0] scaled;
assign scaled = {2'b00, s1} * 11'd3;
always_ff @(posedge clk) begin
  if (rst) begin
    v1 <= 1'b0;
    v2 <= 1'b0;
  end else begin
    v1 <= in_valid;
    v2 <= v1;
    if (in_valid) begin
      s1 <= {1'b0, a} + {1'b0, b};
      t1 <= in_tag;
    end
    if (v1) begin
      s2 <= scaled[7:0];
      t2 <= t1;
    end
  end
end

Accept A=(1,2) at edge 0: afterward s1=3. Accept B=(250,10) at edge 1: s1 becomes 260 while s2 stores A's result 9. A is valid after edge 1 and can transfer at edge 2. B later produces 780 modulo 256, or 12.

Move bubbles through valid registers as well. Holding old v1=1 on a missing input can duplicate a transaction. Reset clears valid state so stale data cannot become a new result. At every boundary, list all companion fields: operation, tag, exception, address, or end-of-packet marker. Check that these fields remain one transaction throughout the pipeline.