10 / 24 · Concept
Latency, throughput, and initiation interval
Calculate single-transaction delay separately from sustained completion rate.
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Finishing sooner differs from finishing more often
Latency measures time from acceptance of one input to delivery of its output. Throughput counts delivered transactions per observation time. Initiation interval, II, is the smallest cycle spacing between new starts. Use cycles or nanoseconds for latency, transactions per cycle or second for throughput, and cycles per transaction for II.
All transfers here occur on rising edges. In a two-register pipeline, an input accepted at edge 0 becomes visible after edge 1 and transfers at edge 2. Acceptance-to-delivery latency is two cycles. Different stages simultaneously handle different transactions, so a full, unstalled pipeline delivers one result per edge. II=1 does not imply latency=1.
| Structure | Delivery latency | II | Sustained unstalled throughput |
|---|---|---|---|
| One-register operator | 1 cycle | 1 | 1 transaction/cycle |
| Two-stage pipeline | 2 cycles | 1 | 1 transaction/cycle |
| Shared four-edge calculation | Depends on interface schedule | Greater than 1 | Less than 1 transaction/cycle |
Include clock period when comparing physical rates. Suppose combinational work takes six nanoseconds and register overhead plus margin takes 0.5 ns. One stage estimates a 6.5 ns period. Balanced three-nanosecond stages estimate 3.5 ns. Both have II=1, giving about 153.8 and 285.7 million transactions per second. Yet single-item delay may increase from 6.5 to seven nanoseconds. These are illustrative calculations, not measured implementation timing.
The slowest stage limits the clock. A five-plus-one split estimates 5.5 ns, worse than a balanced split. Extra registers also add overhead, routing, and control costs; inspect actual implementation timing.
For four inputs accepted at edges 0 through 3, outputs transfer at edges 2 through 5. Startup and drain affect short batches. Specify the measurement window. With stalls, latency varies by transaction, and presented inputs that were never accepted do not count. Record input acceptance, output delivery, and stalled cycles separately before optimizing a suspected bottleneck.
Try it yourself
For a three-stage pipeline with II=1 and a four-nanosecond clock, find sustained throughput and delivery latency. If the first input is accepted at edge 0, at which edge is the fifth output delivered?
Read the explanation
Throughput is 250 million transactions per second and latency is 12 ns. The fifth input is accepted at edge 4 and delivered at edge 7, assuming no stalls.