Altifigence Academy

26 / 32 · Lab

Lab: separate amplification from filtering

Simulate an educational gain stage plus RC pole and state what the model omits.

A deliberately transparent active filter

Place a noninverting gain-2 stage before a 15.9 kΩ, 100 nF low-pass. The amplifier isolates the input from the filter load in this educational model; the output is unloaded. The nominal pole is 100.097448 Hz. At low frequency the voltage gain is approximately 2, at the pole approximately √2, and at ten times the pole approximately 0.199007.

Save active-filter.cir and run ngspice -b active-filter.cir with an available standalone ngspice. Eamp is an ideal voltage-controlled voltage source with finite DC gain 100000. It is not a manufacturer op-amp macro-model.

spice
Ideal noninverting gain 2 followed by isolated RC pole
V1 in 0 DC 0 AC 1 SIN(0 0.05 10)
Rg minus 0 10k
Rf amp minus 10k
Eamp amp 0 in minus 100000
Rfilter amp out 15.9k
Cfilter out 0 100n
.op
.ac dec 40 1 100k
.tran 100u 300m 0 100u
.print ac vm(out) vp(out)
.print tran v(in) v(out)
.save all
.end

The finite open-loop gain makes the closed-loop DC gain 100000/(1+50000), approximately 1.999960. The model has no supply pins, output clipping, GBW pole, slew limit, noise, input bias current, or output-current limit. It therefore cannot qualify a physical 3.3 V amplifier. That omission is intentional so the resistor/capacitor response can be checked independently.

Compare and perturb

For an exact AC checkpoint, replace the sweep with .ac lin 1 100.097448 100.097448. Output magnitude should be approximately 1.414185 and phase −0.785398 rad. Compare magnitude within 0.002 and phase within 0.001 rad. At a 10 Hz, 50 mV peak input, the model's settled output peak is approximately 99.503 mV. Allow the initial transient to settle before measuring amplitude.

Change Rfilter to 31.8 kΩ. The corner halves while the low-frequency gain stays approximately 2. Then connect a 100 kΩ output load and calculate its DC attenuation and shifted pole before rerunning. A buffer before the RC does not isolate the RC from a load connected after it.

Record the ideal-model results and the remaining physical checks as separate items. The next design step would select a device and verify common-mode range, swing, bandwidth, slew, and stability. Refer to the ngspice documentation for dependent-source and analysis syntax.

Try it yourself

If an ideal buffer is inserted after this RC stage, which loading error does it address?

Read the explanation

It can prevent a low-resistance following stage from loading the RC output, provided its input impedance is high enough. Its own bias, capacitance, output limits, and stability still need checking.

Lesson files

active-filter.cir ↓

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