MOSFET bias and the limits of square-law models

Threshold is not a useful current rating

A MOSFET gate controls a channel through electric field. Its ideal DC gate current is zero, but real leakage and gate capacitance remain. Threshold voltage marks a model-defined onset of conduction; it does not guarantee low on-resistance or a specific usable drain current. Analog bias and power switching therefore need different device information.

Use an educational long-channel NMOS square-law model: $I_D=k(V_{GS}-V_T)^2/2$ in saturation, with $V_{DS}\geq V_{GS}-V_T$. Ignore channel-length modulation and body effect for this calculation. Let k = 2 mA/V², VT = 1 V, source grounded, and gate held at 2 V. Overdrive is 1 V, giving ID = 1 mA.

Check the region numerically

Connect the drain to 5 V through 2 kΩ. Drain voltage is 3 V, so VDS = 3 V exceeds the 1 V overdrive. The assumed saturation region is consistent. “Saturation” here is the analog MOSFET current-source region; it is not the same use of the word as BJT saturation or an op amp clipped at its output limit.

The model gives $g_m=k(V_{GS}-V_T)=2$ mS. Ignoring output resistance and an external load, common-source voltage gain is approximately $-g_mR_D=-4$. A 10 mV gate perturbation produces approximately −40 mV drain perturbation around 3 V. This derivative is local and does not describe a large gate sweep.

Detect an invalid assumption

If RD rises to 4.7 kΩ while you assume the same 1 mA, drain voltage would be 0.3 V, below the 1 V overdrive. The saturation equation is no longer self-consistent. Use a triode-region model and solve again rather than accepting the impossible operating point.

Modern short-channel and discrete power MOSFETs often need richer models than this square law. Use actual transfer curves, temperature behavior, capacitance, and SPICE model documentation for a device design. The educational numbers teach model selection and consistency; they do not specify a part for the later sensor capstone.