Lab 02 / 25 MIN

Count, reset and wrap around

Explore synchronous reset and wraparound with a two-bit counter.

What you will learn

Start at 3 and reset on the first rising edge. The sequence is then 0, 1, 2, 3, 0. A synchronous reset changes the value only at a clock edge.

SystemVerilog source

module top (
    input logic clk,
    input logic rst,
    output logic [1:0] count
);
    // Active-high synchronous reset: sampled only at the rising clock edge.
    always_ff @(posedge clk)
        if (rst) count <= 2'b00;
        else count <= count + 2'b01;
endmodule

Run the example

In New analysis, choose Two-state single-clock v1. Set Clock port to clk and the period to 1000ps. Use the values below, run Preflight, then Run RTL simulation and compare the result.

Initial register values (LSB first)

[true,true]

Reset port

rst · Active high · 1 cycle

Maximum cycles / time

5 / 5000ps

[
  {
    "inputs": {}
  },
  {
    "inputs": {}
  },
  {
    "inputs": {}
  },
  {
    "inputs": {}
  },
  {
    "inputs": {}
  }
]

Check your understanding

Why does 0 follow 3 instead of 4?

These labs use two-state, single-clock RTL. Do not add #delay, initial or X/Z testbenches. A completion check records your learning, not an engine run.