Lab 03 / 25 MIN

Move bits through a shift register

Follow serial input as it moves through a three-bit register.

What you will learn

At each rising edge, the previous two low bits of q move left and din enters bit 0. Feed 1, 0, 1, 1 and compare each step.

SystemVerilog source

module top (
    input logic clk,
    input logic rst,
    input logic din,
    output logic [2:0] q
);
    // Old q[1:0] and din are captured together at each rising edge.
    always_ff @(posedge clk)
        if (rst) q <= 3'b000;
        else q <= {q[1:0], din};
endmodule

Run the example

In New analysis, choose Two-state single-clock v1. Set Clock port to clk and the period to 1000ps. Use the values below, run Preflight, then Run RTL simulation and compare the result.

Initial register values (LSB first)

[false,false,false]

Reset port

rst · Active high · 1 cycle

Maximum cycles / time

5 / 5000ps

[
  {
    "inputs": {
      "din": [
        false
      ]
    }
  },
  {
    "inputs": {
      "din": [
        true
      ]
    }
  },
  {
    "inputs": {
      "din": [
        false
      ]
    }
  },
  {
    "inputs": {
      "din": [
        true
      ]
    }
  },
  {
    "inputs": {
      "din": [
        true
      ]
    }
  }
]

Check your understanding

If q is 101 and din is 1, what is the next value?

These labs use two-state, single-clock RTL. Do not add #delay, initial or X/Z testbenches. A completion check records your learning, not an engine run.