Altifigence Academy

15 / 20 · Lab

Lab: backpressure and reset

Execute global pause, result retention and reset of an interrupted job.

Pause logical time as one unit

Our learning array uses global advance. The boundary scheduler and every PE move only when the next logical-step bundle is available. A lane scheduled to be invalid does not require a real operand. Advancing only one stream breaks skew. Independently stalled links need additional buffering and matching rules, beyond this baseline.

The output uses a separate valid/ready contract. Once a result is ready, hold valid, data and job stable until an edge with valid&&ready transfers it exactly once. The simple wrapper starts no new job while an old result remains pending. Consumer readiness need not stop computation when adequate result storage exists.

Save this as stall-lab.mjs and run node stall-lab.mjs. It models a two-term PE plus a result register, requires no packages and prints Stall/reset lab passed.

javascript
import assert from 'node:assert/strict';
let s;
function reset(){s={step:0,acc:0,valid:false,data:0,job:7};}
const pairs=[[-2,3],[4,-5]];
function tick({advance=true,ready=false,rst=false}={}){
 if(rst){reset();return null;}
 if(s.valid){if(!ready)return null;
  const out={data:s.data,job:s.job};s.valid=false;return out;}
 if(advance&&s.step<pairs.length){
  const [a,b]=pairs[s.step];s.acc+=a*b;s.step++;
  if(s.step===pairs.length){s.data=s.acc;s.valid=true;}}
 return null;
}
reset();tick();assert.equal(s.acc,-6);
const held={...s};tick({advance:false});assert.deepEqual(s,held);
tick();assert.equal(s.data,-26);assert.equal(s.valid,true);
const blocked={...s};tick({ready:false});tick({ready:false});
assert.deepEqual(s,blocked);
assert.deepEqual(tick({ready:true}),{data:-26,job:7});
assert.equal(tick({ready:true}),null);
reset();tick();tick({rst:true,advance:false});
assert.deepEqual(s,{step:0,acc:0,valid:false,data:0,job:7});
tick();tick();assert.equal(s.data,-26);
console.log('Stall/reset lab passed');

Interpret the checks

A pause holds the first sum −6 and schedule position. The second term produces −26. Two blocked output edges preserve the result; a ready edge transfers it once. Reset during an incomplete job clears its accumulator, position and result-valid state, so recovery restarts the job.

Adding two global pauses to the four-step 2×2 schedule gives four advance edges and six physical edges. Results and consumed k lists must match the unstalled run. The logical completion formula remains unchanged.

This is a synchronous control reference. Physical reset synchronization and clock-domain crossings require separate design. A reset-aborted job must never report successful completion; clear upstream buffers before restarting. Model success does not establish RTL, installed-app or hardware acceptance.

Try it yourself

Hold valid=1 and ready=0 for three edges, then assert ready. Which signals must hold, how many transfers occur, and what if reset arrives while waiting?

Read the explanation

Hold data, job and valid. Waiting transfers zero results; the ready edge transfers one. Reset discards pending valid state and must not deliver that job as successful. Any cancellation notification needs a separate status contract.

Lesson files

stall-lab.mjs ↓

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