RTL integration review and extensions

Divide core and wrapper responsibilities

The array core handles registered operand forwarding, signed MACs, valid/tags and global advance. The wrapper handles start/clear, matrix dimensions, tile coordinates, skewed boundary supply, masked result collection and output handshakes. Define each responsibility with signal names and an edge contract.

A simple wrapper uses IDLE, CLEAR, RUN, COLLECT and SEND. CLEAR guarantees one initialization edge before data. RUN advances logical steps zero through K+2N−3. Results become complete immediately after the last RUN edge; COLLECT copies them at the following edge. This avoids copying the old accumulator on the same edge as its final nonblocking update.

Work an integration-latency example

For N=K=2, clear occurs at E−1 and computation at E0..E3. Assume E4 copies four results in parallel to a result buffer. A one-result-per-edge output with ready always true sends nineteen, twenty-two, forty-three and fifty on E5..E8 in row-major order. Measuring from clear through final transfer includes ten rising edges E−1..E8, compared with four compute edges. Output blocking extends SEND without changing completed values.

Result payloads need job and global coordinates, plus a defined raw or quantized representation. Do not clear an accumulator until its result is safely copied or consumed. Overlapping the next computation with SEND requires buffer ownership and job separation.

Revisit contracts when extending the design

A pipelined multiplier changes accumulation, tag and completion timing. Reduction tiling needs retained partial sums and a new width analysis. Overlapping jobs needs separate accumulation state. A FIFO stores value, valid and tags as one payload and requires overflow/underflow checks.

The Gemmini architecture documentation offers a primary-source example where local storage and data movement accompany the array. Our state machine and timing example are independently specified learning contracts.

Submit dimensions, widths, a boundary schedule, completion definition, pause/reset policy, output order and scoreboard logs. Node checks establish reference-model behavior. RTL simulation, synthesis, timing closure and product integration need their own executed commands and evidence before claiming success.