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RTL Design: Systolic Arrays

Learning outline

Learning outline
01Matrices and arithmetic contracts
Map dot products to processing elementsConcept
Signed products and accumulator widthConcept
Fixed-point output policyConcept
Check the arithmetic contractCheck
02Processing elements and valid tokens
The contract at one rising edgeConcept
Lab: a signed MAC processing elementLab
Valid flags, tags and flushingConcept
Check processing-element controlCheck
03Arrays and input schedules
Output-stationary and other dataflowsConcept
Lab: a skewed 2×2 arrayLab
Scale to N×N and count completion edgesConcept
Check scheduling and completionCheck
04Tiling, bandwidth and flow control
Tiling and boundary paddingConcept
Bandwidth and useful utilizationConcept
Lab: backpressure and resetLab
Check padding and bandwidthCheck
05Verification and capstone
Scoreboards and invariantsConcept
Design signed and boundary testsConcept
Capstone: a tiled N×N verification modelLab
RTL integration review and extensionsConcept

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