Digital Logic Circuits
Learn how digital circuits select inputs, store state and move data through concepts and hands-on RTL examples.
What you will learn
- Understand combinational logic and input selection with a MUX
- Explore clocks, reset and state changes with a counter
- Follow data movement and previous state in a shift register
- Run SystemVerilog examples and compare waveforms with your predictions
Before you begin
Read the concepts in your browser. For the labs, prepare a Digital Design Studio Desktop project and the permissions to run it. Source and input files are included.
Installation and first launch ↗Curriculum
- Signals and selection
- Bits, signals and portsConcept
Identify inputs, outputs and the meaning of one-bit values.
- Specify the selection with a truth tableConcept
List every input combination and define its expected output.
- The MUX and its observation registerConcept
Distinguish a combinational output from a sampled output.
- Write and run the RTL
- Describe a MUX with a conditional expressionConcept
Connect the select signal and data inputs in RTL.
- MUX simulation labLab
Compare outputs using the provided source and input files.
- Interpret and check
- Input changes and sampling instantsConcept
Track y and sampled_y before and after a clock edge.
- Test the cases that reveal mistakesConcept
Choose cases that reveal reversed selection and sampling errors.
- MUX knowledge checkCheck
Check your understanding of selection and storage.
- Numbers and time
- Bit width and binary valuesConcept
Read the values and bit positions of a two-bit number.
- Clock edges and stateConcept
Separate input changes from register updates.
- The counter and synchronous resetConcept
Compute the next state from the previous state.
- Update state and run the lab
- Compute the next value from the old valueConcept
Read nonblocking assignments and reset priority in the code.
- Counter simulation labLab
Observe incrementing and wraparound after reset.
- Boundaries and debugging
- What follows the maximum value?Concept
Calculate addition beyond the register width.
- Diagnose reset and counting errorsConcept
Check the initial value, reset and first edge in order.
- Counter knowledge checkCheck
Check bit width and wraparound behavior.
- Bits and data flow
- Vector direction and bit indicesConcept
Read q[2:0] and identify the positions selected by a slice.
- Read a serial input over timeConcept
Organize a stream of one-bit inputs into a timeline.
- State changes in a shift registerConcept
Move the previous bits and insert the new input.
- Concatenation and the lab
- Slices and concatenationConcept
Trace how concatenated bits map into the new register.
- Shift-register simulation labLab
Trace the serial input alongside q.
- Latency and debugging
- Follow a bit to the outputConcept
Count the edges as one input bit moves through the stages.
- Check direction, reset and input orderConcept
Use a single-bit pattern to expose reversed connections.
- Shift-register knowledge checkCheck
Compute the next state using the pre-update value.