Line buffers and 3×3 windows

Keep overlapping data nearby

A row-major 3×3 operation needs the current pixel and values from the same column in two preceding rows. Two line delays supply those rows. Horizontal shift registers hold three samples from each row, forming the window. This avoids storing a whole frame, but the earliest samples cannot form a complete window. Stored data and valid output are distinct conditions.

We begin with one channel, valid 3×3, stride one and dilation one. Two width-W row arrays plus an explicit 3×3 window contain 2W+9 sample slots. This is the teaching model's storage, not a universal minimum. Padding, dilation, different strides or multiple channels require a new delay and validity analysis.

Worked arrival sequence

Stream a 4×4 input containing one through sixteen. Zero-based accepted input index ten carries value eleven at row two, column two. The first complete window is [1,2,3;5,6,7;9,10,11]. Value twelve gives [2,3,4;6,7,8;10,11,12]. Values thirteen and fourteen begin a new row and have insufficient horizontal history. Values fifteen and sixteen yield the last two windows.

Thus sixteen accepted inputs produce four windows, at indices [10,11,14,15]. Even at one pixel per cycle, initialization and row boundaries create gaps. Distinguish the full-frame rate 4/16 from instantaneous output rate inside a valid run.

At column zero, reset or invalidate horizontal history. Otherwise a new row can combine its first samples with the preceding row's last columns. Our model clears the horizontal window and suppresses output until column two. It preserves the row delays. Advance row and column counters using accepted pixels rather than elapsed clocks.

At width four, storage is seventeen samples. Unlike a 4H full-frame buffer, it does not grow with frame height. Yet the MAC consumer must still have time to process every complete window, especially across multiple output channels. The next lesson adds transfer control. Follow input, row delays, window and consumer in the supported diagram.