Altifigence Academy

21 / 24 · Concept

Golden models and failure classification

Reference [37,47;67,77] differs from [38,48;68,78]. What would you inspect first and what would you log?

Check values, ordering and time

Correctness includes tensor shape, every output code, channel/spatial ordering, transfer acceptance and completion. Use a wide-integer direct convolution as the golden reference and calculate windows plus flattened dot products through another structure. Less shared code reduces shared failure. Hand-calculated fixtures can catch both models being wrong together.

Compare accumulation,requantization,ReLU and pooling separately. An accumulator mismatch suggests addressing,kernel order,group connectivity,bias initialization or width. Equal accumulators with different output codes suggest scale,zero point,rounding or saturation. Equal values at different coordinates suggest output ordering. Failures only under pauses suggest state advancement or backpressure.

Worked mismatch classification

The 3×3 input [1,2,3;4,5,6;7,8,9] and kernel [1,2;3,4] produce [37,47;67,77]. Result [23,33;53,63] starts with 23 instead of 37, matching the reversed-kernel fixture. Inspect orientation. Result [37,67;47,77] contains the right values at transposed coordinates. Inspect row/column ordering. These are diagnostic clues, not final proof: check the actual addresses and products.

Choose corners for padding tests; a center position never exercises out-of-bounds behavior. Raw-padding errors disappear when zero point is zero, so include a nonzero zero point such as 128 and asymmetric padding. Add signed minimums, large biases and exact rounding ties to expose defects that small positive samples miss.

Retain configuration,scale/zero points,random seed,first mismatching coordinate,expected and actual values. Save the relevant input window and weights. Under pauses,compare accepted input/output records for omissions and duplicates. Equal counts alone do not prove correct order.

Match evidence to scope. The Node exercises verify arithmetic and a simple schedule estimate. SystemVerilog syntax,simulation,synthesis,frequency,power,installed-DDS file handling and model accuracy each require their own execution evidence. Mark unrun items accordingly. The next lab executes corner fixtures; the final lab compares a complete small path and reports explicit measurements.

Try it yourself

Reference [37,47;67,77] differs from [38,48;68,78]. What would you inspect first and what would you log?

Read the explanation

Check bias value/initialization and retained accumulator state because every output is one larger. Log the first initial sum and each product to distinguish addressing errors. A constant difference alone does not prove its cause.

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