Schedules, tails and double buffering

Turn a lower bound into a schedule

A compute bound assumes every useful PE slot can be filled. A schedule must place loads, initialization, MACs, conversion, writing and completion. Splitting the reduction axis across PEs creates partial sums that need combining. Splitting output axes may avoid that combination but leaves idle PEs on output tails. State which axis is parallelized.

Worked reduction tail

One output needs K=9 MACs and two PEs execute two terms per cycle. It needs ceil(9/2)=5 MAC cycles, with one invalid slot in the final cycle. Four outputs processed sequentially use twenty MAC cycles and forty available slots. Thirty-six useful MACs give 90% MAC-slot utilization. Assume one additional combine/write cycle per output, with no overlap: total 24 cycles.

That overhead is a model assumption, not verified RTL latency. Real reduction trees, dependencies and output ports may differ. Relative to all PE slots across 24 cycles, utilization is 36/(2×24)=75%. This denominator differs from the 90% MAC-only figure. The capstone labels these assumptions.

Worked double-buffer overlap

Suppose each tile needs six load cycles, ten compute cycles and two write cycles. Three completely serial tiles need 54 cycles. With separate load/compute resources, double-buffered inputs and weights, and nonconflicting writes, load the first tile for six cycles, then compute three ten-cycle tiles while prefetching successors. Add the last two-cycle write: 38 cycles. Earlier writes are assumed to overlap the following computation.

If computation takes four cycles but loading still takes six, the loader falls behind. Two buffers cannot create bandwidth. Draw ownership transitions so a new load cannot overwrite an active compute buffer. If loads and writes share a bus, recalculate the ideal schedule.

Receiving the last input does not finish the operation. Drain MACs,conversion,activation,pooling and the final accepted result. Specify counter start/end conditions. Software estimates,RTL simulation,synthesized frequency and device measurements are different evidence; this course supplies numerical execution and an explicit schedule estimate.