RTL Design: Systolic Arrays
Build a parameterized matrix multiplication array from signed MAC arithmetic, input skew and processing elements, then verify tiling, flow control and exact edge-by-edge behavior.
What you will learn
- Map matrix indices and dot products to processing elements
- Choose signed product, accumulator and fixed-point output widths
- Schedule output-stationary 2×2 and N×N arrays with skewed inputs
- Specify valid, tags, stalls and reset with an exact edge contract
- Verify tile boundaries, bandwidth and the capstone with a scoreboard
Before you begin
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Installation and first launch ↗ · Downloads ↗Curriculum
- Matrices and arithmetic contracts
- Map dot products to processing elementsConcept
Separate row, column and reduction indices and calculate a small reference matrix.
- Signed products and accumulator widthConcept
Derive an accumulator width from the worst-case operand range.
- Fixed-point output policyConcept
Separate input scale, negative rounding, saturation and wraparound.
- Check the arithmetic contractCheck
Choose accumulator width using the complete reduction length.
- Processing elements and valid tokens
- The contract at one rising edgeConcept
Fix edge numbering, registered forwarding, accumulation and initialization priority.
- Lab: a signed MAC processing elementLab
Use a standalone model to check valid operands, stalls and clear.
- Valid flags, tags and flushingConcept
Distinguish numerical zero, bubbles and tokens from another job.
- Check processing-element controlCheck
Identify the state that must hold during a pause.
- Arrays and input schedules
- Output-stationary and other dataflowsConcept
Compare storage and transport by identifying what stays in the PE.
- Lab: a skewed 2×2 arrayLab
Model one-edge forwarding delays and check every intermediate accumulator.
- Scale to N×N and count completion edgesConcept
Parameterize spatial size N separately from reduction length K.
- Check scheduling and completionCheck
Distinguish final injection from final result availability.
- Tiling, bandwidth and flow control
- Tiling and boundary paddingConcept
Map larger matrices onto a smaller grid and handle zero padding and output masks.
- Bandwidth and useful utilizationConcept
Separate peak MAC capacity from fill, drain, padding and memory costs.
- Lab: backpressure and resetLab
Execute global pause, result retention and reset of an interrupted job.
- Check padding and bandwidthCheck
Distinguish operand validity from result-address validity.
- Verification and capstone
- Scoreboards and invariantsConcept
Check terms, tags, edges and output transfers in addition to the final matrix.
- Design signed and boundary testsConcept
Combine arithmetic, shape and control boundaries beyond one happy-path example.
- Capstone: a tiled N×N verification modelLab
Combine arbitrary N and K with padding and pauses and compare against an independent reference.
- RTL integration review and extensionsConcept
Connect the learning model to RTL interfaces and verification evidence.