RTL Design Fundamentals

Curriculum

1. RTL and module contracts
   • RTL: describing concurrent circuitsConcept

     Separate software execution order from parallel hardware structure and specify state, next state and observation times.

   • Signals and ports: a contract for width, direction and timeConcept

     Read interfaces and distinguish the checking criteria for combinational and state outputs.

   • Modules, ports and instances: connections as contractsConcept

     Compose combinational modules using named connections while checking single drivers and hierarchy boundaries.

   • Check: combinational and stored outputsCheck

     Distinguish when inputs change from when a register is observed.

2. Types, widths, signedness and expressions
   • logic, wire, X/Z and explicit bit widthsConcept

     Understand why a type declaration does not determine storage and verify literals, comparisons, extensions and unknown values.

   • Vector indexing, bit order and signednessConcept

     Separate bit numbering, serial transmission order and arithmetic interpretation when reading datapaths.

   • Widths of slices, concatenations and replicationsConcept

     Build datapaths by calculating concatenated widths and the conditions for preserving values.

   • Two's complement, sign extension and overflowConcept

     Use equations and counterexamples to distinguish signed bit-pattern interpretation from addition overflow.

   • Check: range and explicit extensionCheck

     Check the input and output widths of an adder together.

3. Complete combinational RTL and verification
   • Combinational RTL and complete assignmentsConcept

     Express the same function with a conditional operator and always_comb, and find omissions that infer latches.

   • Encoders and priority: choosing one of several requestsConcept

     Distinguish the input assumption of a one-hot encoder from a priority encoder's valid and selection outputs.

   • MUX verification: exhaustive tests and propertiesConcept

     Check combinational input coverage separately from storage behavior, and minimize counterexamples.

   • Design check: selection equivalence and observation timingCheck

     Distinguish checks covered by a truth table from those requiring clock observations.

4. State, assignments and reset priority
   • Flip-flops, enable and control priorityConcept

     Define hold, load and reset through next-state equations and avoid unintended clock gating.

   • Nonblocking assignments and simultaneous state updatesConcept

     Separate old and next values to interpret pipeline and counter RTL correctly.

   • Modulo and saturating counters, and terminal pulsesConcept

     Specify maximum-value handling and the exact cycle of the terminal-count signal.

   • Lab: verify counter reset, wraparound and invariantsLab

     Compare every rising-edge state with a reference model and separate the effects of initialization, reset and width.

   • Design check: boundaries of width, priority and wraparoundCheck

     Use a specified state-transition contract to reason about boundaries and simultaneous controls.

5. Parameters and static structure generation
   • parameter, localparam, $clog2 and boundary configurationsConcept

     Separate run-time inputs from static configuration and design counter widths and termination for N=1 and non-power-of-two values.

   • generate: building static circuits with loopsConcept

     Use genvar and generate-if to create named circuit instances and check bus lane placement.

   • function automatic and reusable expressionsConcept

     Write functions that consume no simulation time and check return width, signedness and reference-model independence.

   • Check: N=1 and bit widthCheck

     Separate a declaration that guarantees minimum width from a counter’s actual number of states.

6. Testbenches and independent verification
   • Waveform sampling times and causalityConcept

     Read waveforms by separating combinational settling, clock capture and event order.

   • Lab: a testbench that reports its own failuresLab

     Separate DUT, stimulus, reference model and checks, then test reset, enable and wraparound at race-free observation times.

   • Verification plans, coverage and independent reference modelsConcept

     Distinguish passing tests from satisfying the specification, and link boundaries, crossed conditions and minimal counterexamples to a verification plan.

   • Counter debugging and minimal counterexamplesConcept

     Design short tests that distinguish reset, enable and wrap-boundary errors.

   • Check: reference models and racesCheck

     Choose expectations independent of the DUT and a post-edge checking time.

7. Module composition and integrated lab
   • State machines: separating state, transitions and outputsConcept

     Build an FSM from a specification table and compare Moore/Mealy outputs, illegal states and request policies.

   • Capstone: an overlapping 101 pattern detectorConcept

     Apply state minimization, input validity, registered outputs and independent reference checking in one design.

   • Ready/valid and a one-entry elastic bufferConcept

     Design lossless, duplicate-free transfers and simultaneous input/output in a datapath that can stall.

   • Multiply-add pipelines and data alignmentConcept

     Split arithmetic at register boundaries and keep data, valid, and side operands aligned to the same transaction.

   • Integrated lab: periodic pulses and an enabled accumulatorLab

     Specify inter-module transfers using previous values and compare enable stalls, consecutive pulses and simultaneous reset against a reference model.

8. Tool diagnostics and the scope of results
   • Setup, hold and timing budgetsConcept

     Separate maximum and minimum path delays and calculate hold requirements independently of clock frequency.

   • Clock-domain boundaries and metastabilityConcept

     Understand the limits of a two-stage synchronizer and distinguish single-bit levels, short pulses and multibit transfers.

   • Compile, lint and synthesis: what diagnostics establishConcept

     Fix the source list, top module and language mode and distinguish syntax errors, width warnings, latches and functional verification.

   • Execution records and continuing into DDS practiceConcept

     Bundle source, inputs, expected values, failure conditions and tool versions into reproducible practice evidence.

   • Final check: functional passes and execution evidenceCheck

     Distinguish local tool results from acceptance evidence for free DDS practice.