RTL Design: Datapaths & Pipelines
Specify numeric and cycle contracts, then design an ALU, controller, pipeline, and ready-valid buffering. Four runnable reference-model labs check arithmetic boundaries, stalls, FIFOs, and ordering before a streaming-compute capstone.
What you will learn
- Distinguish widths, signedness, carry, and overflow contracts
- Schedule register transfers, FSM control, and synchronous memory
- Calculate latency, throughput, and initiation interval
- Handle ready-valid stalls and FIFO boundaries without loss
- Build scoreboard checks covering hazards and reset
- Verify a streaming-compute capstone with standalone models
Before you begin
These browser exercises use educational models; they do not compile or run HDL. To run the supplied source separately, follow the Digital Design Studio guide for your operating system and sign in when the operation requires it.
Installation and first launch ↗ · Downloads ↗Curriculum
- Numeric and arithmetic contracts
- Turn an equation into a datapath contractConcept
Specify widths, acceptance events, and valid results alongside the arithmetic.
- Widths, sign extension, and overflowConcept
Use numeric examples to distinguish interpretation, extension, and narrowing.
- Lab: an eight-bit ALU reference modelLab
Check ADD, SUB, AND, XOR, carry, and borrow in a standalone executable.
- Check: carry versus signed overflowCheck
Distinguish numeric boundaries under unsigned and signed interpretation.
- Register transfers and control
- Read register transfers at clock edgesConcept
Separate old and next state, and trace how enables preserve stored values.
- Schedule shared resources with an FSMConcept
Accumulate four values with one adder while defining state transitions and capture.
- Timing contracts for memory requests and responsesConcept
Distinguish synchronous reads, delayed tags, and same-address collisions.
- Check: preserving a completed resultCheck
Separate DONE-state delivery from acceptance of the next request.
- Pipeline timing and throughput
- Store the complete transaction at pipeline boundariesConcept
Split sum-and-scale arithmetic while keeping valid, tag, and widths aligned.
- Latency, throughput, and initiation intervalConcept
Calculate single-transaction delay separately from sustained completion rate.
- Lab: trace two stages and bubblesLab
Calculate next state from old state and compare output tags, values, and edges.
- Check: what II=1 meansCheck
Avoid confusing stage count with sustained throughput.
- Ready-valid flow control
- Acceptance events and stability during stallsConcept
Assign source and sink responsibilities and preserve stalled payloads.
- Design a one-slot elastic registerConcept
Accept into an empty slot or replace a simultaneously consumed item.
- Lab: check 1024 stall patternsLab
Exercise hold, replacement, and emptying with all ten-cycle ready patterns.
- Check: counting a stalled transactionCheck
Distinguish valid duration from actual handshake count.
- FIFO and hazard boundaries
- FIFO empty, full, and simultaneous transfersConcept
Separate occupancy from pointers and specify boundary push/pop behavior.
- Dependencies, resource hazards, and forwardingConcept
Compare stalls and forwarding when an operation needs an earlier result.
- Maintain transaction accounting through flush and resetConcept
Separate cancellation from delivery and align valid state with expected queues.
- Check: replacement in a full FIFOCheck
Calculate occupancy and ordering for simultaneous push and pop.
- Verification and a streaming calculator
- Combine a scoreboard with local invariantsConcept
Check values, ordering, occupancy, and stall stability from accepted transactions.
- Capstone lab: a FIFO and two-stage streaming calculatorLab
Connect a depth-two input FIFO, two elastic stages, and a scoreboard.
- Measure performance and review the designConcept
Specify observation windows, diagnose stalls, and bound model evidence.
- Final check: lossless stalls and drainCheck
Combine arithmetic, outstanding accounting, and completion conditions.