RTL Design: CNN Accelerators
Learn convolution indexing and integer numerical contracts, then streaming windows, PE mapping and tiling. Verify a runnable reference and a small inference path while separating values, schedule estimates and traffic.
What you will learn
- Calculate convolution shapes and indices including stride, padding, dilation and channels
- Specify fixed-point units, scales, zero points, accumulator width, rounding and saturation
- Compare direct convolution with an im2col golden model
- Generate windows with line buffers and transfer acceptance that preserves paused state
- Calculate PE reuse, tile storage, traffic and schedule assumptions
- Report numerical results and evidence limits for a small inference path
Before you begin
These browser exercises use educational models; they do not compile or run HDL. To run the supplied source separately, follow the Digital Design Studio guide for your operating system and sign in when the operation requires it.
Installation and first launch ↗ · Downloads ↗Curriculum
- The inference contract
- Inference and trainingConcept
If only the output channels increase from three to six, how do MAC count and stored bias count change?
- Convolution and cross-correlationConcept
What are cross-correlation and reversed-kernel results for [1,2;4,5] with kernel [1,0;0,-1]?
- Shapes, stride, padding and dilationConcept
For H=7,R=3,stride 2,top pad 0,bottom pad 1,dilation 2, calculate Ho and the input coordinate for h=1,r=2.
- Check: shape and MAC countCheck
Use N=1,C=2,H=W=5,M=3,a 3×3 kernel,stride 2,padding one on all sides,dilation one. What are output shape and MAC count?
- The numerical contract
- Fixed-point bits and unitsConcept
Multiply 0.5 and −1.25 at F=4, then add bias 0.25 at F=8. What are accumulator code and real value?
- Scale and zero pointConcept
For sx=0.25,zx=128, what are the padding code and the real value of q=132? What bias code represents 0.75 with sw=0.5?
- Accumulator width, rounding and saturationConcept
Are eighteen signed bits sufficient for nine signed-int8 products with zero bias?
- Lab: execute the quantization contractLab
Quantize −40 with the same uint8 settings. What are its code and dequantized value, and which assertion would you add?
- Reference operators
- Direct convolution referenceConcept
For inputs [2,3], weights [4,−1] and bias one, what wrong result occurs if bias is added once per input-channel iteration?
- im2col and matrix multiplicationConcept
For H=W=4,C=1 and a valid 3×3 kernel, calculate original input elements, P,K and expanded patch elements.
- Connecting ReLU and max poolingConcept
With uint8 output zero point 100, apply ReLU and 2×2 max pooling to [98,103;101,97].
- Check: output processing orderCheck
Apply multiplier 0.5,zy=0,nearest-even rounding,int8 saturation,ReLU and 2×2 max pooling to accumulators [−1,2;3,−4]. What is the final code?
- Streaming window generation
- Line buffers and 3×3 windowsConcept
For W=8,H=6, calculate storage slots, first valid accepted-input index and total windows.
- Ready/valid and stalled stateConcept
The output stage holds A with out_ready=0 while input B is valid. What must the stage and producer do at the next edge?
- Lab: windows that survive pausesLab
If cycles zero,one,two are paused instead and all inputs are eventually accepted, do window values or count change? What is the total cycle count?
- Check: first-window timingCheck
A 4×4, width-four, valid 3×3 generator accepts no input in the first four cycles, then one pixel per cycle. What are the first window's accepted-input index and elapsed cycle, both zero-based?
- Mapping to PEs and memory
- PEs, dataflow and MAC reuseConcept
Map P=3,M=2,K=8 onto four output-stationary PEs. What are MAC cycles and useful MAC-slot utilization, excluding writes?
- Tiles, halos and partial sumsConcept
For Th=Tw=2,Tc=1,Tm=2,a 3×3 kernel,stride two,dilation one, calculate single-buffer input/weight/32-bit-sum/bias bytes.
- Bandwidth and compute boundsConcept
For 1152 MACs and 224 bytes, use eight PEs but keep bandwidth at 0.5 bytes/cycle. What is the perfect-overlap lower bound?
- Schedules, tails and double bufferingConcept
For K=10,four outputs,three PEs and one extra cycle per output, calculate modeled cycles and MAC-only utilization.
- Verification and a measurable capstone
- Golden models and failure classificationConcept
Reference [37,47;67,77] differs from [38,48;68,78]. What would you inspect first and what would you log?
- Lab: challenge the corner casesLab
In the padding fixture, replace every kernel weight by one. What is the first output and why is a center-only test insufficient?
- Capstone: a small inference path and reportLab
Keep K=9,four outputs and one extra cycle per output but use three PEs. What are total modeled cycles and MAC-only slot utilization?
- Final check: claims and evidenceCheck
The capstone Node run verifies numerical agreement, 36 MACs, a 24-cycle schedule model and 90% MAC-slot use. Which completion statement is accurate?