数字设计In preparation
RTL Design Fundamentals
Express circuit behavior in RTL and connect reusable modules into a complete design.
SystemVerilogModule designSimulation
你将学到什么
- Use signals, bit widths and operators deliberately
- Write distinct combinational and sequential logic
- Design module interfaces and parameters
- Check behavior using input scenarios and waveforms
建议先修课程
Digital Logic Circuits ↗课程大纲
- Signals and SystemVerilog expressions
- Combinational and sequential RTL
- Modules and interfaces
- Simulation and design checks