`timescale 1ns/1ps
// Bounded N=2, K=2 array; one job, full signed sum, no output quantization.
// Inject A(i,k) at logical edge k+i and B(k,j) at k+j.
// Clear completes before E0. Final matrix is observable after E3.
module systolic_2x2 #(
  parameter integer W = 8,
  parameter integer AW = 2*W + 1
) (
  input logic clk, reset, clear, advance,
  input logic signed [W-1:0] a_left0, a_left1, b_top0, b_top1,
  input logic [1:0] a_valid, b_valid,
  input logic a0_k, a1_k, b0_k, b1_k,
  output wire signed [AW-1:0] c00, c01, c10, c11,
  output wire done, protocol_error
);
  wire signed [W-1:0] a01, a11, b10, b11;
  wire av01, av11, bv10, bv11;
  wire ak01, ak11, bk10, bk11;
  wire d00, d01, d10, d11, e00, e01, e10, e11;
  wire [1:0] count00, count01, count10, count11;
  assign done = d00 && d01 && d10 && d11;
  assign protocol_error = e00 || e01 || e10 || e11;

  signed_mac_pe #(.W(W),.K(2),.AW(AW)) pe00 (
    .clk(clk),.reset(reset),.clear(clear),.advance(advance),
    .a_in(a_left0),.b_in(b_top0),.a_valid_in(a_valid[0]),.b_valid_in(b_valid[0]),
    .a_k_in(a0_k),.b_k_in(b0_k),.a_out(a01),.b_out(b10),
    .a_valid_out(av01),.b_valid_out(bv10),.a_k_out(ak01),.b_k_out(bk10),
    .acc(c00),.count(count00),.done(d00),.protocol_error(e00)
  );
  signed_mac_pe #(.W(W),.K(2),.AW(AW)) pe01 (
    .clk(clk),.reset(reset),.clear(clear),.advance(advance),
    .a_in(a01),.b_in(b_top1),.a_valid_in(av01),.b_valid_in(b_valid[1]),
    .a_k_in(ak01),.b_k_in(b1_k),.a_out(),.b_out(b11),
    .a_valid_out(),.b_valid_out(bv11),.a_k_out(),.b_k_out(bk11),
    .acc(c01),.count(count01),.done(d01),.protocol_error(e01)
  );
  signed_mac_pe #(.W(W),.K(2),.AW(AW)) pe10 (
    .clk(clk),.reset(reset),.clear(clear),.advance(advance),
    .a_in(a_left1),.b_in(b10),.a_valid_in(a_valid[1]),.b_valid_in(bv10),
    .a_k_in(a1_k),.b_k_in(bk10),.a_out(a11),.b_out(),
    .a_valid_out(av11),.b_valid_out(),.a_k_out(ak11),.b_k_out(),
    .acc(c10),.count(count10),.done(d10),.protocol_error(e10)
  );
  signed_mac_pe #(.W(W),.K(2),.AW(AW)) pe11 (
    .clk(clk),.reset(reset),.clear(clear),.advance(advance),
    .a_in(a11),.b_in(b11),.a_valid_in(av11),.b_valid_in(bv11),
    .a_k_in(ak11),.b_k_in(bk11),.a_out(),.b_out(),
    .a_valid_out(),.b_valid_out(),.a_k_out(),.b_k_out(),
    .acc(c11),.count(count11),.done(d11),.protocol_error(e11)
  );
endmodule