Altifigence Academy
Conception numériqueIn preparation

RTL Design Fundamentals

Express circuit behavior in RTL and connect reusable modules into a complete design.

SystemVerilogModule designSimulation

Ce que vous apprendrez

  • Use signals, bit widths and operators deliberately
  • Write distinct combinational and sequential logic
  • Design module interfaces and parameters
  • Check behavior using input scenarios and waveforms

Cours préalable recommandé

Digital Logic Circuits ↗

Programme

  1. Signals and SystemVerilog expressions
  2. Combinational and sequential RTL
  3. Modules and interfaces
  4. Simulation and design checks

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