Digital Logic Circuits
Learn how digital circuits select inputs, store state and move data through concepts and hands-on RTL examples.
आप क्या सीखेंगे
- Explain combinational circuits using binary numbers, gates and Boolean algebra
- Calculate adder, comparator and signed arithmetic boundary cases
- Implement a MUX, counter and shift register and compare waveforms
- Complete a small design using state machines, timing constraints and a verification plan
शुरू करने से पहले
सिद्धांत ब्राउज़र में पढ़ें। प्रयोगों के लिए Digital Design Studio Desktop प्रोजेक्ट और चलाने की अनुमति तैयार रखें। सोर्स और इनपुट फ़ाइलें शामिल हैं।
स्थापना और पहली शुरुआत ↗पाठ्यचर्या
- Foundations of digital logic
- Binary and hexadecimalअवधारणा
Represent the same value in binary and hexadecimal.
- Gates and truth tablesअवधारणा
Compare the output rules of AND, OR, NOT and XOR.
- Boolean algebra and De Morgan’s lawsअवधारणा
Check whether different expressions produce the same output.
- Decoders and enable signalsअवधारणा
Turn a binary address into one active output.
- Signals and selection
- Bits, signals and portsअवधारणा
Identify inputs, outputs and the meaning of one-bit values.
- Specify the selection with a truth tableअवधारणा
List every input combination and define its expected output.
- The MUX and its observation registerअवधारणा
Distinguish a combinational output from a sampled output.
- Write and run the RTL
- Describe a MUX with a conditional expressionअवधारणा
Connect the select signal and data inputs in RTL.
- MUX simulation labप्रयोग
Compare outputs using the provided source and input files.
- Interpret and check
- Input changes and sampling instantsअवधारणा
Track y and sampled_y before and after a clock edge.
- Test the cases that reveal mistakesअवधारणा
Choose cases that reveal reversed selection and sampling errors.
- MUX knowledge checkजाँच
Check your understanding of selection and storage.
- Arithmetic circuits and state
- Half adders and full addersअवधारणा
Compute sum and carry separately, then chain them.
- Signed values and overflowअवधारणा
Interpret the same bits as unsigned and two’s complement.
- Comparators and boundary conditionsअवधारणा
Connect equality and magnitude comparisons to boundary tests.
- Flip-flops and clock enableअवधारणा
Specify the priority of reset, enable and hold.
- Numbers and time
- Bit width and binary valuesअवधारणा
Read the values and bit positions of a two-bit number.
- Clock edges and stateअवधारणा
Separate input changes from register updates.
- The counter and synchronous resetअवधारणा
Compute the next state from the previous state.
- Update state and run the lab
- Compute the next value from the old valueअवधारणा
Read nonblocking assignments and reset priority in the code.
- Counter simulation labप्रयोग
Observe incrementing and wraparound after reset.
- Boundaries and debugging
- What follows the maximum value?अवधारणा
Calculate addition beyond the register width.
- Diagnose reset and counting errorsअवधारणा
Check the initial value, reset and first edge in order.
- Counter knowledge checkजाँच
Check bit width and wraparound behavior.
- Bits and data flow
- Vector direction and bit indicesअवधारणा
Read q[2:0] and identify the positions selected by a slice.
- Read a serial input over timeअवधारणा
Organize a stream of one-bit inputs into a timeline.
- State changes in a shift registerअवधारणा
Move the previous bits and insert the new input.
- Concatenation and the lab
- Slices and concatenationअवधारणा
Trace how concatenated bits map into the new register.
- Shift-register simulation labप्रयोग
Trace the serial input alongside q.
- Latency and debugging
- Follow a bit to the outputअवधारणा
Count the edges as one input bit moves through the stages.
- Check direction, reset and input orderअवधारणा
Use a single-bit pattern to expose reversed connections.
- Shift-register knowledge checkजाँच
Compute the next state using the pre-update value.
- Connect and verify circuits
- Combinational delay and timing budgetsअवधारणा
Distinguish functional simulation from timing verification.
- Design a small state machineअवधारणा
Describe state, input and next state in a transition table.
- Verification plans and failure tracesअवधारणा
Define expected results for normal, boundary and reset cases.
- Capstone: serial pattern detectorअवधारणा
Design and check a state machine that detects the pattern 101.