Digital Logic Circuits

Programme

1. Foundations of digital logic
   • Binary and hexadecimalConcept

     Represent the same value in binary and hexadecimal.

   • Gates and truth tablesConcept

     Compare the output rules of AND, OR, NOT and XOR.

   • Boolean algebra and De Morgan’s lawsConcept

     Check whether different expressions produce the same output.

   • Decoders and enable signalsConcept

     Turn a binary address into one active output.

2. Signals and selection
   • Bits, signals and portsConcept

     Identify inputs, outputs and the meaning of one-bit values.

   • Specify the selection with a truth tableConcept

     List every input combination and define its expected output.

   • The MUX and its observation registerConcept

     Distinguish a combinational output from a sampled output.

3. Write and run the RTL
   • Describe a MUX with a conditional expressionConcept

     Connect the select signal and data inputs in RTL.

   • MUX simulation labTravaux pratiques

     Compare outputs using the provided source and input files.

4. Interpret and check
   • Input changes and sampling instantsConcept

     Track y and sampled_y before and after a clock edge.

   • Test the cases that reveal mistakesConcept

     Choose cases that reveal reversed selection and sampling errors.

   • MUX knowledge checkVérification

     Check your understanding of selection and storage.

5. Arithmetic circuits and state
   • Half adders and full addersConcept

     Compute sum and carry separately, then chain them.

   • Signed values and overflowConcept

     Interpret the same bits as unsigned and two’s complement.

   • Comparators and boundary conditionsConcept

     Connect equality and magnitude comparisons to boundary tests.

   • Flip-flops and clock enableConcept

     Specify the priority of reset, enable and hold.

6. Numbers and time
   • Bit width and binary valuesConcept

     Read the values and bit positions of a two-bit number.

   • Clock edges and stateConcept

     Separate input changes from register updates.

   • The counter and synchronous resetConcept

     Compute the next state from the previous state.

7. Update state and run the lab
   • Compute the next value from the old valueConcept

     Read nonblocking assignments and reset priority in the code.

   • Counter simulation labTravaux pratiques

     Observe incrementing and wraparound after reset.

8. Boundaries and debugging
   • What follows the maximum value?Concept

     Calculate addition beyond the register width.

   • Diagnose reset and counting errorsConcept

     Check the initial value, reset and first edge in order.

   • Counter knowledge checkVérification

     Check bit width and wraparound behavior.

9. Bits and data flow
   • Vector direction and bit indicesConcept

     Read q[2:0] and identify the positions selected by a slice.

   • Read a serial input over timeConcept

     Organize a stream of one-bit inputs into a timeline.

   • State changes in a shift registerConcept

     Move the previous bits and insert the new input.

10. Concatenation and the lab
    • Slices and concatenationConcept

      Trace how concatenated bits map into the new register.

    • Shift-register simulation labTravaux pratiques

      Trace the serial input alongside q.

11. Latency and debugging
    • Follow a bit to the outputConcept

      Count the edges as one input bit moves through the stages.

    • Check direction, reset and input orderConcept

      Use a single-bit pattern to expose reversed connections.

    • Shift-register knowledge checkVérification

      Compute the next state using the pre-update value.

12. Connect and verify circuits
    • Combinational delay and timing budgetsConcept

      Distinguish functional simulation from timing verification.

    • Design a small state machineConcept

      Describe state, input and next state in a transition table.

    • Verification plans and failure tracesConcept

      Define expected results for normal, boundary and reset cases.

    • Capstone: serial pattern detectorConcept

      Design and check a state machine that detects the pattern 101.